Apple M-Series Performance
Analyzing the TBDR (Tile-Based Deferred Rendering) architecture of Apple Silicon through the WebGPU Metal backend.
| Chip | GFLOPS (Est) | Mem Bandwidth |
|---|---|---|
| M1 Base | 2600 | 68 GB/s |
| M2 Max | 13600 | 400 GB/s |
Analyzing the TBDR (Tile-Based Deferred Rendering) architecture of Apple Silicon through the WebGPU Metal backend.
| Chip | GFLOPS (Est) | Mem Bandwidth |
|---|---|---|
| M1 Base | 2600 | 68 GB/s |
| M2 Max | 13600 | 400 GB/s |